R12 S8 Nil-Linked Law Graph Preregistration

Status: source/theory freeze before the full CPU falsifier or any neural board Parent: confirmed S7 learned Cayley law compiler Claim class: bounded whole-source grounding, model-owned event schedule, and nil-terminated recurrent execution

Motivation

S7 confirms exact contextual induction and recurrent execution of unseen cyclic laws, but its evaluator receives structured law cards and ordered event records, then advances them with a host for loop. S4 v5 separately confirms whole-source known-operation parsing, while S5 confirms a learned local transition law. The next honest intervention is therefore not a wider arithmetic model. It must remove S7's structured card/event/schedule interface.

S8 compiles a natural-language source once into a discrete nil-linked law graph. Every executable choice must be present in model output:

initial-state symbols and query position;
operation-card names and both witnessed outputs;
event entity and operation-card pointers;
an entry-event pointer;
one next-event pointer per event; and
a nil link that terminates execution.

Node records are stored in random order. The runtime may follow only the emitted entry/next links; source order, row order, a gold depth, and a host event list are unavailable. Each visited event invokes the frozen S7 generator/compiler and updates the categorical state. The result is read from the emitted query.

This is a project-original architectural hypothesis, not a literature novelty claim. It replaces autoregressive verbal chain-of-thought with an executable pointer graph whose links jointly encode active-step selection and halt.

Exact resource boundary

Model-owned

source-to-roster and initial-state grounding;
law-card witness extraction;
event entity and operation-card binding;
entry and next-event pointers;
nil termination;
query grounding;
the already confirmed learned cyclic successor dynamics.

Architectural

discrete argmax and equality;
validation that a predicted graph is one nil-terminated path;
graph traversal with a node-count safety bound;
the confirmed S7 bounded cyclic compiler;
categorical pop_insert state mutation;
the finite admitted modulus set.

Malformed, cyclic, multiply visited, or stranded graphs fail closed. The host may validate and traverse model pointers but may not repair them, infer order from source positions, supply depth, select an operation card, or fill a missing terminal link.

CPU theorem and falsifier

Before any board seed, the independent reference executor and graph executor must be compared over:

all 120 hidden coordinate bindings at modulus 5;
128 deterministic bindings each at moduli 7 and 11;
64 deterministic bindings at modulus 13;
eight depth-three-through-eight programs per binding;
random node storage permutations and at least two laws per program.

Immutable CPU gates:

treatment state and answer are exactly 100%;
changing node storage IDs leaves every result unchanged;
at least 95% of paths differ from storage order;
storage-order execution is below 40% exact state;
reversed links are below 40% exact state;
deranged operation cards are below 40% exact state;
one-witness unit completion is below 40% exact state;
state reset is below 40% exact state; and
early nil termination is below 40% exact state.

Failure rejects the interface before GPU use. A passing CPU result authorizes only a committed board builder and one fresh development experiment.

Neural architecture and parameter cap

The protected 300k Shohin trunk and confirmed S7 dynamics remain frozen. A trainable graph compiler may add at most 16,000,000 parameters, keeping the complete system below 150M. The preferred form is late-layer adapters plus factorized span, binding, link, entry, nil, and query heads. Wider recurrent language-model decoding is not permitted in v1 because it would reintroduce serialization errors and obscure the resource comparison.

Training may supervise graph fields on training sources. It may not supervise final state, final answer, recurrent transitions, development laws, confirmation laws, or any result produced by the S7 executor. The S7 generator may receive only successor cells and zero anchors under the new hidden coordinate binding.

Future board custody

Only after source, CPU report, and this preregistration are committed may board and training seeds be drawn. The builder must produce:

disjoint training, development, and sealed-confirmation law pools;
arbitrary hidden symbol bindings generated after source commit;
disjoint entity names, operation nonces, and language renderers;
random event-node storage order independent of source/execution order;
balanced depths three through eight and at least two laws per program;
zero exact prompt, normalized prompt, or 13-gram overlap across splits;
no structured graph, depth, state, or answer in score-time model input;
2,048 development and 2,048 sealed-confirmation programs;
access counters beginning at zero/zero.

The confirmation file may not be opened by training, development evaluation, diagnostics, or board audits that reveal labels.

Frozen neural arms

Gold-graph upper bound: frozen S7 execution from the gold graph; quarantined.
S8 treatment: learned graph fields, links, nil, cards, and query; frozen S7 execution.
Favorable ordinary sequence parser: same trunk and comparable head budget, but emits source-ordered event records and receives host list traversal.
Storage-order shortcut: ignores predicted links and executes node records in storage order.
Reversed-link intervention: preserves every node/card field but reverses the linked path.
Card derangement: rotates witnessed outputs across operation names.
One-witness intervention: replaces the second witness with a unit default.
State reset: restores initial state before each visited event.
Early-nil intervention: terminates after the first predicted event.
Shuffled graph-label control: matched compiler trained on a fixed label permutation.

Immutable development gates

All must pass on the sole development read:

graph validity at least 95%;
exact complete graph at least 90%;
exact event count and nil termination at least 98%;
exact recurrent state at least 85%;
answer accuracy at least 90%;
every depth exact state at least 75%;
gold-graph state and answers exactly 100%;
treatment no more than 10 state points below gold graph;
treatment no more than three state points below the favorable ordinary parser;
storage-order shortcut below 40% state;
reversed links reduce state by at least 40 points;
card derangement reduces state by at least 50 points;
one-witness completion reduces state by at least 30 points;
state reset reduces state by at least 20 points;
early nil reduces state by at least 30 points;
shuffled-label exact graph below 10%;
graph reindexing leaves treatment states bit-identical;
operation-nonce recoding leaves treatment states bit-identical;
all hashes, access counters, training exclusions, and parameter counts match.

Passing authorizes one unchanged-weight sealed confirmation under separately committed gates. Failure closes S8 v1. No width, threshold, renderer, board, training-label, or rescore repair is allowed on the opened development board.

Claim on a pass

A confirmed pass would establish that a sub-150M Shohin stack can ground a whole source into an executable discrete law graph, choose and order its own bounded reasoning steps, terminate with its own nil link, infer unseen cyclic operation laws from demonstrations, and reuse learned state dynamics recurrently.

It would still not establish arbitrary algebra, free-form theorem proving, unbounded planning, unconstrained natural language, or an autonomous agent. The finite cyclic substrate, hard graph runtime, safety bound, and state mutation would remain explicit architectural priors.